1 CPMF-1200-S080B rev. a CPMF-1200-S080B z -f e t tm silicon carbide mosfet n-channel enhancement mode bare die features ? industry leading r ds(on) ? high speed switching ? low capacitances ? easy to parallel ? simple to drive benefts ? higher system effciency ? reduced cooling requirements ? avalanche ruggedness ? increase system switching frequency applications ? solar inverters ? motor drives ? military and aerospace package die part number package CPMF-1200-S080B die g d s s g d note: 1. assumes a thermal resistance junction to case of 0.4 c/w . v ds = 1200 v r ds(on) = 80 m ? q g = 90.8 nc maximum ratings symbol parameter value unit test conditions note i d continuous drain current 46 a v gs @20v, t c = 25?c 1 25.9 v gs @20v, t c = 100?c i dpulse pulsed drain current 85 a pulse width t p limited by t jmax t c = 25?c, tp = 1ms 1 e as single pulse avalanche energy 2.2 j i d = 20a, v dd = 50 v, l = 9.5 mh e ar repetitive avalanche energy 1.5 j t ar limited by t jmax i ar repetitive avalanche current 20 a i d = 20a, v dd = 50 v, l = 3 mh t ar limited by t jmax v gs gate source voltage -5/+25 v p tot power dissipation 275 w t c =25?c 1 t j , t stg operating junction and storage temperature -55 to +135 ?c t l solder temperature 260 ?c 1.6mm (0.063) from case for 10s www.datasheet.co.kr datasheet pdf - http://www..net/
2 CPMF-1200-S080B rev. a electrical characteristics symbol parameter min. typ. max. unit test conditions note v (br)dss drain-source breakdown voltage 1200 v v gs = 0v, i d = 100a v gs(th) gate threshold voltage 2.5 4 v v ds = v gs , i d = 1ma, t j = 25oc 2 1.7 v ds = v gs , i d = 1ma, t j = 135oc i dss zero gate voltage drain current 1 100 a v ds = 1200v, v gs = 0v, t j = 25oc 10 250 v ds = 1200v, v gs = 0v, t j = 135oc i gss gate-source leakage current 250 na v gs = 20v, v ds = 0v r ds(on) drain-source on-state resistance 80 110 m ? v gs = 20v, i d = 20a, t j = 25oc 110 130 v gs = 20v, i d = 20a, t j = 135oc g fs transconductance 7.3 s v ds = 20v, i ds = 20a, t j = 25oc fg. 3 6.7 v ds = 20v, i ds = 20a, t j = 135oc c iss input capacitance 1915 pf v gs = 0v v ds = 800v f = 1mhz v ac = 25mv fg. 5 c oss output capacitance 120 c rss reverse transfer capacitance 13 t d(on)i turn-on delay time 17.2 ns v dd = 800v v gs = -2/20v i d = 20a r g = 6.8 l = 856 h per jedec24 page 27 fg. 11 t r rise time 13.6 t d(off)i turn-off delay time 62 t f fall time 35.6 e on turn-on switching loss (25oc) ( 135oc) 530 422 j e off turn-off switching loss (25oc) ( 135oc) 320 329 j r g internal gate resistance 5 v gs = 0v, f = 1mhz , v ac = 25mv note: 2. the recommended on-state vgs is +20v and the recommended off -state vgs is between -2v and -5v reverse diode characteristics symbol parameter typ. max. unit test conditions note v sd diode forward voltage 3.5 v v gs = -5v, i f = 10a, t j = 25oc 3.1 v gs = -2v, i f = 10a, t j = 25oc t rr reverse recovery time 220 ns v gs = -5v, i f = 20a, t j = 25oc v r = 800v, d i f /d t= 100a/ s fg. 12,13 q rr reverse recovery charge 142 nc i rrm peak reverse recovery current 2.3 a gate charge characteristics symbol parameter typ. max. unit test conditions note q gs gate to source charge 23.8 nc v dd = 800v i d =20a v gs = -2/20v per jedec24-2 fg.8 q gd gate to drain charge 43.1 q g gate charge total 90.8 www.datasheet.co.kr datasheet pdf - http://www..net/
3 CPMF-1200-S080B rev. a 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 25 35 45 55 65 75 85 95 105 115 125 135 0 5 10 15 20 25 30 35 0 2 4 6 8 10 12 14 16 40 60 80 100 120 i d (a) 0 20 40 0 2 4 6 8 10 12 14 16 18 20 v ds (v) 0 10 20 30 40 50 60 70 80 90 0 2 4 6 8 10 12 14 16 18 20 fig 2. typical output characteristics t j = 135oc typical performance fig 4. normalized on-resistance vs. temperature fig 5a and 5b. typical capacitance vs. drain C source voltage fig 1. typical output characteristics t j = 25oc v gs =16v v gs =14v v gs =12v v gs =10v v gs =18v v gs =20v v gs =16v v gs =14v v gs =12v v gs =10v v gs =18v v gs =20v figure 3. typical transfer characteristics t = 135 c t = 25 c v gs =20v 1.0e-09 1.0e - 08 capacitance (f) c iss c oss v gs = 0 v f = 1 mhz 1.0e-11 1.0e-10 0 20 40 60 80 100 120 140 160 180 200 capacitance (f) v ds (v) c rss 1.0e-09 1.0e - 08 capacitance (f) c iss c oss v gs = 0 v f = 1 mhz 1.0e-11 1.0e-10 0 100 200 300 400 500 600 700 800 capacitance (f) v ds (v) c rss i d (a) v ds (v) i d (a) v ds (v) normalized r ds(on) t ?c i d (a) v gs (v) v ds (v) capacitance (f) v ds (v) capacitance (f) www.datasheet.co.kr datasheet pdf - http://www..net/
4 CPMF-1200-S080B rev. a 0 100 200 300 400 500 600 25 35 45 55 65 75 85 95 105 115 125 135 0 100 200 300 400 500 600 25 35 45 55 65 75 85 95 105 115 125 135 5 10 15 20 25 v gs (v) -5 0 5 10 15 20 25 0 20 40 60 80 100 v gs (v) gate charge (nc) typical performance fig 8. typical gate charge characteristics @ 25c fig 6. inductive switching energy(turn-on) vs. t fig 7. inductive switching energy(turn-off) vs. t i d =20a v dd =800v v gs = -2/20v r g = 11.8 total v dd = 800v i d = 20a v gs = -2/20v r g = 11.8 total v dd = 800v i d = 20a 1000 1500 2000 2500 10 15 20 25 v ds (v) i ds (a) i ds v ds 0 500 0 5 0 0.001 0.002 0.003 0.004 0.005 0.006 time (s) e as = 2.20 j fig 9. typical avalanche waveform t ?c t ?c switching loss (j) switching loss (j) www.datasheet.co.kr datasheet pdf - http://www..net/
5 CPMF-1200-S080B rev. a 10% irr v cc t rr irr ic vpk tx 10% v cc qrr= trr id dt tx diode reverse recovery energy diode recovery waveforms erec= t2 id dt t1 t1 t2 v gs(off) v gs(on) i d(off) i d(on) t d(on)i t d(off)i t f t ri pulse duration t w input (v i ) output (i d ) input pulse rise time input pulse fall time 90% 50% 10% 90% 50% 10% 10% 10% 90% 90% t on(i) t off(i) 800v + - 42.3f 856h cmf20120d c2d10120d 10a, 1200v sic schottky clamped inductive switch testing fixture fig 10. switching waveform test circuit fig 13. body diode recovery test 800v 42.3f 856h cmf20120d cmf20120d + - fig 11. switching test waveform times fig 12. body diode recovery waveform d.u.t. d.u.t. www.datasheet.co.kr datasheet pdf - http://www..net/
6 CPMF-1200-S080B rev. a fig 15. theoretical avalanche waveform fig 14. avalanche test circuit e a = 1/2l x i d 2 www.datasheet.co.kr datasheet pdf - http://www..net/
7 this product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body nor in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines, cardiac defbrillators or similar emergency medical equipment, aircraft navigation or communication or control systems, air traffc control systems, or weapons systems. copyright ? 2010-2011 cree, inc. all rights reserved. the information in this document is subject to change without notice. cree, the cree logo is a registered trademark of cree, inc. 7 CPMF-1200-S080B rev. a cree, inc. 4600 silicon drive durham, nc 27703 usa tel: +1.919.313.5300 fax: +1.919.313.5451 www.cree.com/power * the levels of environmentally sensitive, persistent biologically toxic (pbt), persistent organic pollutants (pop), or otherwise restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with eu directive 2002/95/ec on the restriction of the use of certain hazardous substances in electrical and electronic equipment (r ohs), as amended through april 21, 2006. * the die-on-tape method of delivering these sic die may be considered a means of temporary storage only. due to an increase in adhesion over time, die stored for an extended period may affx too strongly to the tape. these die should be stored in a temperature-controlled nitrogen dry box soon after receipt. cree will further recommend that all die be removed from tape to a waffe pack, to a similar storage medium, or used in production within 2 C 3 weeks of delivery to assure 100% release of all die without issues. part number package CPMF-1200-S080B die g d s s g d s g d chip dimensions parameter typ unit die dimensions (l x w) 4.08 x 4.08 mm exposed source pad metal dimensions 0.98 x 2.09 (x 2) mm gate pad dimensions 0.84 x 0.60 mm chip thickness 365 25 m frontside (source) metallization (al) 4 m frontside (gate) metallization (al) 4 m backside (drain) metallization (ni/ag) 0.8 / 0.6 m mechanical parameters www.datasheet.co.kr datasheet pdf - http://www..net/
8 CPMF-1200-S080B rev. a 2.5v applications information: the cree sic dmosfet has removed the upper voltage limit of silicon mosfets. however, there are some differences in characteristics when compared to what is usually expected with high voltage silicon mosfets. these differences need to be carefully addressed to get maximum beneft from the sic dmosfet. in general, although the sic dmosfet is a superior switch compared to its silicon counter - parts, it should not be considered as a direct drop-in replacement in existing appli - cations. there are two key characteristics that need to be kept in mind when applying the sic dmosfets; modest transconductance and no turn-off tail. the modest trans - conductance requires that v gs needs to be 20v to optimize performance. this can be seen the output and transfer characteristics shown in figures 1-3. the modest transconductance also affects the transition where the device behaves as a voltage controlled resistance to where it behaves as a voltage controlled current source as a function of v ds . the result is that the transition occurs over higher values of v ds than is usually experienced with si mosfets and igbts. this might affect the operation anti-desaturation circuits, especially if the circuit takes advantage of the device entering the constant current region at low values of forward voltage. the modest transconductance needs to be carefully considered in the design of the gate drive circuit. the frst obvious requirement is that the gate driver be capable of a 22v (or higher) swing. the recommended on state v gs is +20v and the rec - ommended off state v gs is between -2v to -5v. please carefully note that although the gate voltage swing is higher than typical silicon mosfets and igbts, the to - tal gate charge of the sic dmosfet is considerably lower. in fact, the product of gate voltage swing and gate charge for the sic dmosfet is lower than comparable silicon devices. the gate voltage must have a fast dv/dt to achieve fast switching times which indicates that a very low impedance driver is necessary. lastly, the fdelity of the gate drive pulse must be carefully controlled. the nominal threshold voltage is 2.3v and the device is not fully on (dv ds /dt 0) until the v gs is above 16v. this is a noticeably wider range than what is typically experienced with sili - con mosfets and igbts. the net result of this is that the sic dmosfet has a somewhat lower noise margin. any excessive ringing that is present on the gate drive signal could cause unintentional turn-on or partial turn-off of the device. the gate resistance should be carefully selected to insure that the gate driv e pulse is adequately dampened. to frst order, the gate circuit can be approximated as a www.datasheet.co.kr datasheet pdf - http://www..net/
9 CPMF-1200-S080B rev. a r loop l loop c gate v pulse as shown, minimizing l loop minimizes the value of r loop needed for critical dampening. minimizing l loop also minimizes the rise/fall time. therefore, it is strongly recommended that the gate drive be located as close to the sic dmosfet as possible to minimize l loop . an external resistance of 6.8 was used to characterize this device. lower values of external gate resistance can be used so long as the gate pulse fidelity is maintained. in the event that no external gate resistance is used, it is suggested that the gate current be checked to indirectly verify that there is no ringing present in the gate circuit. this can be accomplished with a very small current transformer. a recommended setup is a two - stage curren t transformer as shown below: the two stage current transformer first stage consists of 10 turns of awg 30 wire on a small high permeability core. a ferroxcube 3e27 material is recommended. the second stage is a small wide bandwidth current transformer, such as the tektronix ct - 2. l astly, a separate source return should be used for the gate drive as shown below: 1 l c 2 r loop gate loop gate loop loop c l 2 r vcc sic dmosfet vee + - gate driver t1 gate drive input ig sense as shown, minimizing l loop minimizes the value of r loop needed for critical dampening. minimizing l loop also minimizes the rise/fall time. therefore, it is strongly recommended that the gate drive be located as close to the sic dmosfet as possible to minimize l loop . an external resistance of 6.8 was used to characterize this device. lower values of external gate resistance can be used so long as the gate pulse fdelity is maintained. in the event that no external gate resistance is used, it is suggested that the gate current be check ed to indirectly verify that there is no ringing present in the gate circuit. this can be accomplished with a very small current transformer. a recommended setup is a two-stage current transformer as shown below: the two stage current transformer frst stage consists of 10 turns of awg 30 wire on a small high permeability core. a ferroxcube 3e27 material is recommended. the second stage is a small wide bandwidth current transformer, such as the tektronix ct-2. lastly, a separate source return should be used for the gate drive as shown below: www.datasheet.co.kr datasheet pdf - http://www..net/
10 CPMF-1200-S080B rev. a stray inductance on source lead causes load di/dt to be fed back into gate drive which causes the following: ? switch di/dt is limited ? could cause oscillation load current load current sic dmos r gate sic dmos r gate l stray kelvin gate connection with separate source return is highly recommended drive drive 20v 20v a signifcant beneft of the sic dmosfet is the elimination of the tail current observ ed in silicon igbts. however, it is very important to note that the current tail does provide a certain degree of parasitic dampening during turn-off. additional ringing and overshoot is typically observed when silicon igbts is replaced with sic dmosfets. the additional voltage overshoot can be high enough to destroy the device. therefore, it is critical to manage the output interconnection par asitics (and snubbers) to keep the ringing and overshoot from becoming problematic. esd ratings esd test total devices sampled resulting classifcation esd-hbm all devices passed 1000v 2 (>2000v) esd-mm all devices passed 400v c (>400v) esd-cdm all devices passed 1000v iv (>1000v) www.datasheet.co.kr datasheet pdf - http://www..net/
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